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| INDEX MX23L8111 8M-BIT MASK ROM(8/16 BIT OUTPUT) FEATURES * Bit organization - 1M x 8 (byte mode) - 512K x 16 (word mode) * Fast access time - Random access: 100ns (max.) - Page access: 50ns (max.) * Current - Operating: 20mA - Standby: 20uA * Supply voltage - 100ns @3.0V ~ 3.6V - 120ns @2.7V ~ 3.6V * Package - 44 pin SOP (500mil) - 42 pin PDIP (600mil) - 48 pin TSOP (type 1) - 44 pin TSOP (type 2) ORDER INFORMATION Part No. Access Time MX23L8111MC-10 MX23L8111MC-12 MX23L8111PC-10 MX23L8111PC-12 MX23L8111TC-10 MX23L8111TC-12 MX23L8111RC-10 MX23L8111RC-12 MX23L8111YC-10 MX23L8111YC-12 100ns 120ns 100ns 120ns 100ns 120ns 100ns 120ns 100ns 120ns Page Access Time 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 50ns 60ns 44 pin SOP 44 pin SOP 42 pin PDIP 42 pin PDIP 48 pin TSOP 48 pin TSOP 48 pin RTSOP 48 pin RTSOP 44 pin TSOP 44 pin TSOP Package Note: 48-TSOP and 48-RTSOP support word mode only, not for byte mode. PIN CONFIGURATION 44 SOP/44TSOP NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE D0 D8 D1 D9 D2 D10 D3 D11 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 NC NC A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC 42PDIP A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE VSS OE D0 D8 D1 D9 D2 D10 D3 D11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 NC A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS D15/A-1 D7 D14 D6 D13 D5 D12 D4 VCC 48 TSOP (for word mode only) NC A16 A15 A14 A13 A12 A11 A10 A9 A8 NC VSS NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VSS VSS D15 D7 D14 D6 D13 D5 D12 D4 VCC VCC NC D11 D3 D10 D2 D9 D1 D8 D0 OE VSS VSS 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 MX23L8111 (Normal Type) MX23L8111 MX23L8111 48 Reverse TSOP (for word mode only) VSS VSS D15 D7 D14 D6 D13 D5 D12 D4 VCC VCC NC D11 D3 D10 D2 D9 D1 D8 D0 OE VSS VSS 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 NC A16 A15 A14 A13 A12 A11 A10 A9 A8 NC VSS NC A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE MX23L8111 (Reverse Type) P/N:PM0412 REV. 1.9,JAN. 22, 1999 1 INDEX MX23L8111 PIN DESCRIPTION Symbol A0~A18 D0~D14 D15/A-1 CE OE Byte VCC VSS NC Pin Function Address Inputs Data Outputs D15(Word Mode)/LSB Address (Byte Mode) Chip Enable Input Output Enable Input Word/Byte Mode Selection Power Supply Pin Ground Pin No Connection MODE SELECTION CE OE Byte D15/A-1 D0~D7 D8~D15 Mode H L L L X H L L X X H L X X Input High Z High Z D0~D7 High Z High Z High Z Byte Power Stand-by Active Active Active Output D0~D7 D8~D15 Word BLOCK DIAGRAM A0/(A-1) A2 A3 A18 CE BYTE OE Address Buffer Memory Array Page Buffer Page Decoder Double Word Output Buffer D0 D15/(D7) ABSOLUTE MAXIMUM RATINGS Item Voltage on any Pin Relative to VSS Ambient Operating Temperature Storage Temperature Symbol VIN Topr Tstg Ratings -1.3V to VCC+2.0V (Note) 0 to 70 C C -65 to 125 C C Note: Minimum DC voltage on input or I/O pins is -0.5V. During voltage transitions, inputs may undershoot VSS to -1.3V for periods of up to 20ns. Maximum DC voltage on input or I/O pins is VCC+0.5V. During voltage transitions, input may overshoot VCC to VCC+2.0V for periods of up to 20ns. P/N:PM0412 REV. 1.9, JAN. 22, 1999 2 INDEX MX23L8111 DC CHARACTERISTICS (Ta = 0C ~ 70C, VCC = 3.3V10%) Item Output High Voltage Output Low Voltage Input High Voltage Input Low Voltage Input Leakage Current Output Leakage Current Operating Current Standby Current (TTL) Standby Current (CMOS) Input Capacitance Output Capacitance Symbol VOH VOL VIH VIL ILI ILO ICC1 ISTB1 ISTB2 CIN COUT MIN. 24V 2.2V -0.3V MAX. 0.4V VCC+0.3V 0.8V 5uA 5uA 20mA 1mA 20uA 10pF 10pF Conditions IOH = -0.4mA IOL = 1.6mA 0V, VCC 0V, VCC f=10MHz, all output open CE=VIH CE> VCC - 0.2V Ta = 25 f = 1MHZ C, Ta = 25 f = 1MHZ C, AC CHARACTERISTICS (Ta = 0C ~ 70C, VCC = 3.3V10%) Item Read Cycle Time Address Access Time Chip Enable Access Time Page Mode Access Time Output Enable Time Output Hold After Address Output High Z Delay Symbol tRC tAA tACE tPA tOE tOH tHZ 23L8111-10 MIN. MAX. 100ns 100ns 100ns 50ns 50ns 0ns 20ns 23L8111-12 MIN. MAX. 120ns 120ns 120ns 60ns 60ns 0ns 20ns Note:Output high-impedance delay (tHZ) is measured from OE or CE going high, and this parameter guaranteed by design over the full voltage and temperature operating range - not tested. AC Test Conditions IOH (load)=-0.4mA Input Pulse Levels Input Rise and Fall Times Input Timing Level Output Timing Level Output Load 0.4V~2.4V 10ns 1.4V 1.4V See Figure DOUT IOL (load)=1.6mA C<100pF Note:No output loading is present in tester load board. Active loading is used and under software programming control. Output loading capacitance includes load board's and all stray capacitance. P/N:PM0412 REV. 1.9, JAN. 22, 1999 3 INDEX MX23L8111 TIMING DIAGRAM RANDOM READ ADD ADD tACE ADD tRC ADD CE OE tOE tOH VALID tHZ VALID tAA DATA VALID PAGE READ A3-A18 VALID ADD (A-1),A0,A1,A2 1'st ADD tAA 2'nd ADD tPA VALID VALID 3'rd ADD DATA VALID Note: CE, OE are enable. Page size is 8 words in 16-bit mode, 16 bytes in 8-bit mode. P/N:PM0412 REV. 1.9, JAN. 22, 1999 4 INDEX MX23L8111 REVISION HISTORY Revision 1.8 1.9 Description Add new 44pin TSOP(type2) Output hold after address (tOH) spec is revised as 0ns(min.) 120ns speed grade's voltage range is revised as 2.7V~3.6V Page P3 P1 Date Jul/17/1998 JAN/22/1999 P/N:PM0412 REV. 1.9, JAN. 22, 1999 5 INDEX MX23L8111 MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: TEL:+886-3-578-8888 FAX:+886-3-578-8887 EUROPE OFFICE: TEL:+32-2-456-8020 FAX:+32-2-456-8021 JAPAN OFFICE: TEL:+81-44-246-9100 FAX:+81-44-246-9105 SINGAPORE OFFICE: TEL:+65-747-2309 FAX:+65-748-4090 TAIPEI OFFICE: TEL:+886-3-509-3300 FAX:+886-3-509-2200 MACRONIX AMERICA, INC. TEL:+1-408-453-8088 FAX:+1-408-453-8488 CHICAGO OFFICE: TEL:+1-847-963-1900 FAX:+1-847-963-1909 http : //www.macronix.com MACRONIX INTERNATIONAL CO., LTD. reserves the rignt to change product and specifications without notice. 6 |
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